1. Field
Exemplary embodiments of the present invention relate to a memory device and a memory system including the memory device.
2. Description of the Related Art
FIG. 1 is a block view illustrating a general memory device, such as a Dynamic Random Access Memory (DRAM) device.
FIG. 1 shows a single memory bank and related circuits in the memory device. Referring to FIG. 1, the memory device includes a memory array 110, a row circuit 120, and a column circuit 130. The memory array 110 includes a plurality of memory cells. The row circuit 120 activates a word line selected based on a row address RADD. The column circuit 130 accesses (i.e., reads or writes) data of a bit line selected based on a column address CADD.
A row fuse circuit 140 stores a repair row address REPAIR_RADD as a row address corresponding to a failed memory cell among the memory cells of the memory array 110. A row comparator 150 compares the repair row address REPAIR_RADD stored in the row fuse circuit 140 with the row address RADD inputted from outside of the memory device. If the repair row address REPAIR_RADD is the same as the row address RADD, the row comparator 150 controls the row circuit 120 to activate a redundancy word line instead of the word line designated by the row address RADD. In short, the row (word line) corresponding to the repair row address REPAIR_RADD stored in the row fuse circuit 140 is replaced with a redundancy row (word line).
An RACT signal is enabled in response to an active command, which activates a word line in the memory array 110, and is disabled in response to a precharge command, which deactivates a word line. Also, IRD refers to a read command, while IWR refers to a write command.
Generally, laser fuses are used in the row fuse circuit 140. The laser fuses store data of a logic ‘high’ level or a logic ‘low’ level depending on whether the fuses are cut. The laser fuses may be programmed in the wafer stage, but once the wafer is mounted in a package, it is not possible to program the laser fuses. Also, the laser fuses may not be designed in a small area due to pitch limitations.
To overcome these drawbacks, a non-volatile memory, such as an e-fuse array circuit, a NAND flash memory, a NOR flash memory, a Magnetic Random Access Memory (MRAM), a Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), a Resistive Random Access Memory (ReRAM), a Phase Change Random Access Memory (PC-MRAM) and the like is included in a memory device, and a repair data or a failure address is stored in the non-volatile memory.
FIG. 2 is a block view Illustrating a non-volatile memory circuit used to store repair data in a memory device.
Referring to FIG. 2, the memory device includes a plurality of memory banks BK0 to BK3, a non-volatile memory circuit 201, and registers 210_0 to 210_3 provided for the memory banks, respectively, and storing repair data.
The non-volatile memory circuit 201 substitutes the row fuse circuit 140. The non-volatile memory circuit 201 stores repair data, which are failed addresses, corresponding to all the memory banks BK0 to BK3. The non-volatile memory circuit 201 may be one selected from the group of non-volatile memories including an e-fuse array circuit, a NAND flash memory, a NOR flash memory, a Magnetic Random Access Memory (MRAM), a Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), a Resistive Random Access Memory (ReRAM), a Phase Change Random Access Memory (PC-MRAM) and the like.
Each of the registers 210_0 to 210_3 provided for the memory banks BK0 to BK3 stores the repair data of the memory bank corresponding thereto. For example, the register 210_0 stores the repair data of the memory bank BK0, and the register 210_2 stores the repair data of the memory bank BK2. The registers 210_0 to 210_3 are formed of latch circuits, and the registers 210_0 to 210_3 may store the repair data while power is supplied thereto. The repair data to be stored in the registers 210_0 to 210_3 are transmitted from the non-volatile memory circuit 201.
The repair data stored in the non-volatile memory circuit 201 are not directly used but are stored in the registers 210_0 to 210_3 and then used. This is because the non-volatile memory circuit 201 is formed in an array and thus it takes a predetermined time to read the data stored in the non-volatile memory circuit 201. Since the data stored in an array-type non-volatile memory circuit 201 may not be read instantly, it is impossible to perform a repair operation by directly using the data stored in the non-volatile memory circuit 201. Therefore, a boot-up operation where the repair data stored in the non-volatile memory circuit 201 are transmitted to and stored in the registers 210_0 to 210_3 is performed, and then after the boot-up operation, the repair operation is performed using the data stored in the registers 210_0 to 210_3.
When the row fuse circuit 140 formed of laser fuses is replaced by the non-volatile memory circuit 201 and the registers 210_0 to 210_3, it is possible to repair failures that are detected after the wafer stage. Meanwhile, researchers and industry are developing a technology for repairing failures detected after the fabrication of a memory device by accessing the non-volatile memory circuit 201 even after the fabrication of the memory device is completed (e.g., even after the product is sold).